1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, more particularly, relates to a semiconductor device in which a connected portion between a capacitor using a ferroelectric material or a highly dielectric material and a plug formed under the capacitor is improved, and a method of manufacturing the same.
2. Description of the Related Art
In recent years, development of a ferroelectric memory which is a nonvolatile memory using a ferroelectric thin film has been advanced. In order to miniaturize a cell of the ferroelectric memory and increase its capacitance, a capacitor on plug (COP) structure has been considered.
FIG. 8 shows a conventional COP structure. In the drawing, reference numeral 81 denotes a silicon substrate, 82 denotes a source/drain diffusion layer of a MOS transistor, 83 denotes a silicon oxide film, 84 denotes a silicon nitride film, 85 denotes a plug formed of tungsten (W) or polycrystalline silicon, 86 denotes a capacitor lower electrode formed of platinum (Pt), 87 denotes a PZT (PbZrXTi1-XO3) film (capacitor dielectric film), and 88 denotes a capacitor upper electrode formed of Pt.
In the COP structure, a capacitor is provided on the plug 85 connected to the source/drain diffusion layer 82 of the MOS transistor, and a cell size can be reduced in the same manner as in a stacked capacitor of a DRAM.
In a process of this type of COP structure, after the plug 85 is formed, heat treatment is carried out a plurality of times under an oxidizing atmosphere. As one example, there is a heat treatment at a high temperature of about 600° C. or more, for crystallizing the PZT film 87 formed in an amorphous form. A reason why the PZT film 87 is crystallized is that ferroelectric materials such as PZT do not develop ferroelectricity in an amorphous state.
Other examples of the heat treatment under the oxidizing atmosphere after the plug 85 is formed include: a treatment for recovering damage of the capacitor caused by reactive ion etching (RIE) processing in an integration process of the capacitor, that is, damage caused in the PZT film 87 at a time when the PZT film formed on the whole surface is RIE-processed to form the PZT film 87; and a heat treatment for recovering the damage by plasma in a reducing atmosphere at the time of forming an interlayer insulating film in CVD in a process for forming the film in the CVD for an SiO2 hard mask for RIE processing.
A reason why the heat treatment for crystallizing the PZT film 87 or for recovering the damage is carried out under the oxidizing atmosphere is that oxygen deficit of the PZT film 87 accompanying the heat treatment is inhibited.
Here, Pt which is the material of the capacitor lower electrode 86 does not have an oxygen barrier property. Therefore, when W is used as the material of the plug 85 in the heat treatment under the oxidizing atmosphere, the plug 85 is oxidized by oxygen permeated in the capacitor lower electrode 86 to form W oxide. Accordingly, contact between the plug 85 and the capacitor lower electrode 86 becomes defective, or a plug structure itself is destroyed by volume expansion of the plug 85, and the capacitor peels. On the other hand, when polycrystalline Si is used as the material of the plug 85, Si oxide is formed, and therefore a contact defect is similarly generated.
Therefore, it has been proposed that oxidation of the plug 85 be prevented by a barrier layer formed of TiAlN, TiN, and TaSiN. However, this type of barrier layer has a film thickness of about 100 nm or more, and is a factor for hindering miniaturization.
This problem also exists in a stacked DRAM which takes a process of forming a capacitor after forming the plug and in which highly dielectric materials such as Ta2O5 and (Ba,Sr)TiO3 are used in a capacitor dielectric film.